This invention relates to a transfer control unit for controlling data transfer between processors in a parallel processor system or the like, and relates to a processor element and a data transferring method using the same.
Recently, a parallel processor system is focused on as a favorite candidate of a super computer for the next generation. In the parallel processor system, the total performance largely depends on the ability of transferring data between processors, thus a high speed, high performance transfer control unit which controls data transfer is contemplated.
An example of conventional transfer control unit and processor element is described below, with reference to FIG. 8. FIG. 8 shows a construction of a processor element 18 and a transfer control unit 3 for a parallel processing. The processor element 18 has a processor 1, a memory 2 and the transfer control unit 3. Each of them 1-3 is connected in common to one another via an address bus 5 and a data bus 6. The processor 1 sends out a transfer enable pulse Ste for allowing the transfer control unit 3 to transfer a data.
The transfer control unit 3 includes an address register capable of being set from outside, an address generating part 11 for generating an address according to an output signal Sar From the address register 10, a buffer 14 for temporarily storing input/output data, and output and input ports 15a, 15b for communicating to an external peripheral circuit 40.
An operation of the transfer control unit 3 and processor element 18 with the above construction is explained next. The processor 1 executes a process, while accessing the memory 2 via the address bus 5. When a sequential process is executed, the processor only performs such an operation basically. However, in parallel systems, such an operation cannot be performed smoothly because of frequent communication between the processor element 18 and outside. Therefore, in the parallel systems, usually, the address generating part 11 in the transfer control unit 3 sends out an address to the address bus 5 to access to the memory 2. The data proceeds to the data bus 6, the buffer 14 then to the output port 15a when being sent, and proceeds to the input port 15b, the buffer 14, then to the data bus 6 when being received. As a result, the bus is occupied for the communication with the outside, thus the time for which the processor 1 can use the bus is reduced.
A high speed operation in case the processor element 18 sends a data outside, using a transfer enable pulse Ste is described. The processor 1 sends out the data to the data bus 6 and asserts the transfer enable pulse Ste. Receiving the signal Ste, the transfer control unit 3 fetches the data from the data bus 6 and temporarily stores into the buffer 14, then sends out the data from the output port 15a to the outside thereafter. The data flows in a direction of a broken line.
In this mode, the address generating part is not used basically. When the buffer 14 of the transfer control unit 3 cannot store the data because of being full, or the like, it is required to read the data from the memory 2 thereafter. The address generating part 11 is used in such a case.
Accordingly, memory-write and data sending are carried out concurrently, thus the data bus 6 is effectively used. The above operation is disclosed in the report of the institute of electronics, information and communication engineers (IEICE), Spring Conference 1990, D-110 and the report of IEICE, Integrated Circuits and Devices, ICD 89-152.
With the above construction, however, a hardware for generating the transfer enable pulse is required. Therefore, it is required to design an exclusive processor, or to equip a separate hardware around a processor for general purpose. This means that a processor for general purpose cannot be used without a peripheral hardware. Therefore, a high speed LSI which appears successively to the market cannot be used, which involves a problem upon designing of a system.
This invention has its object of providing a high speed transfer control unit responsive to a processor for general purpose and of providing a processor element using it.
A transfer control unit in this invention comprises: a buffer for temporarily storing data; an address register capable of being written from outside; an address generating part, connected to the address register, for sequentially generating addresses to access based on a value of the address register; a comparator for comparing an address generated in the address generating part with an address inputted from outside to output a coincidence signal when the addresses coincide with each other; and a control part, also referred to as a controller, connected to the comparator, the buffer and the address generating part, for commanding the buffer to store an outside data and commanding the address generating part to proceed to a next address according to the coincidence signal from the comparator.
With the above construction, in the transfer control unit, the comparator compares the inside address generated in the address generator with the outside address inputted from the outside and outputs the coincidence signal when the addresses coincide with each other, and the control part commands the buffer to store the outside data and commands the address generator to proceed to a next address. Accordingly, without the transfer enable pulse inputted from an external circuit, it is possible to transfer a data to the peripheral circuits after the temporarily data storage only by controlling the inside of the transfer control unit, thus performing the high-speed transfer.
The control part in the transfer control unit includes: a counter which is connected to the comparator, which counts coincidence times at receiving the coincidence signal outputted from the comparator, and which is reset to an initial value when it counts up to a preset value; and a signal generating part, connected to the counter, the buffer, and the address generating part, for generating a signal for commanding the buffer to store the outside data and commanding the address generating part to proceed to a next address when the count of the counter reaches to the preset value.
With the above construction, the counter counts the coincidence times when the control part receives the coincidence signal from the comparator. When the count of coincidence signal reaches to the preset value, the signal generating part commands to store the data and to proceed to a next address. Accordingly, the transfer work region is unnecessary even in a case with plural memory accesses at calculation, thus saving the memory.
When the signal generating part is so arranged to be connected to an output side of the comparator, and to command the buffer to store the outside data and command the address generating part to proceed to a next address when count of the counter reaches to the preset value and the signal generating part receives the coincidence signal from the comparator, further high-speed signal process is performed, since the signal generating part commands to store the data and to proceed to a next address when the count of the coincidence times reaches to the preset value and the coincidence signal is received.
A processor element in the present invention comprises a memory, a processor, and a transfer control unit which are connected to one another via a common bus, wherein the transfer control unit includes: a buffer for temporarily storing data; an address register capable of being written from outside; an address generating part, connected to the address register, for sequentially generating addresses to access based on a value of the address register; a comparator for comparing an address generated in the address generating part with an address inputted from outside to output a coincidence signal when the addresses coincide with each other; and a control part, connected to the comparator, the buffer and the address generating part, for commanding the buffer to store an outside data and commanding the address generating part to proceed to a next address according to the coincidence signal from the comparator, and wherein the processor is connected to the comparator of the transfer control unit, outputs an address signal to the comparator and writes a data into an address in the memory accessed by the address generating part.
As a result, data transfer according to the above operation is performed in the transfer control unit according to the memory access signal from the processor via the bus. Therefore, high speed transfer is performed without separately providing a device for outputting a transfer enable pulse and an exclusive processor.
A part of the memory serves as a transfer region, and the processor sets addresses corresponding to the transfer region to the address register of the transfer control unit, and writes a data into the transfer region at a data transfer.
Accordingly, a part of the memory region is used as the transfer region, thus performing high speed transfer and saving the memory.
A method of transferring a data in a transfer control unit in the present invention having a buffer for temporarily storing a data, an address register capable of being written from outside, and an address generating part for generating an address based on a value of the address register, comprises the steps of: comparing an address generated in the address generating part with an address inputted from outside; outputting a coincidence signal when the addresses coincide with each other; and according to the coincidence signal, commanding the buffer to store an outside data and commanding the address generating part to proceed to a next address.